1. Field of the Invention
The present invention relates generally to package assembly technology, and more particularly to a method for joining two or more lead frames in a chip stack package or a package stack, a method for forming a chip stack package, and a chip stack package.
2. Description of the Related Art
Developments in semiconductor technology and high demands from consumers have created a trend in the electronics industry towards higher memory capacity and smaller footprints. To meet these demands, stack techniques such as stacking semiconductor chips or stacking packages have been introduced.
The package stack has the advantage of reliability since each assembled package has passed both functional and reliability tests. Further, the chip stack package has the advantage of having a reduced size since all of the chips are assembled together in a single package. A conventional chip stack package, typically referred to as a dual-die package (DDP), is shown in FIG. 1. The dual-die package 100 has two semiconductor chips, e.g., a lower semiconductor chip 10 and an upper semiconductor chip 30. The dual-die package 100 also has two lead frames, e.g., a lower lead frame 20 and an upper lead frame 40. The lower and upper lead frames 20 and 40 are joined together by thermo-compression so that the semiconductor chips 10 and 30 face back-to-back. For a good joint, portions of the lead frames 20 and 40 are pre-plated with plating layers 28 and 48, respectively, which can be seen in FIG. 2.
When the pre-plated lead frames 20 and 40 are joined by thermo-compression, the interface between the plating layers 28 and 48 may increase, as is shown in FIG. 2, which reduces the reliability that the semiconductor chips 10 and 30 are tightly connected. Such a drawback can result from oxidation of the plating layers 28 and 48. The oxidation may be promoted by the heat applied during thermo-compression and thus the plating layers 28 and 48 may not be properly joined.
One approach to overcome the above problem is to perform a solder dipping process after the package assembly has been formed. Referring to FIG. 1, the solder dipping process forms a solder coating layer 90 on an outer lead 47 of the upper lead frame 30 as well as on the joining portions of the lead frames 20 and 40. The solder coating layer 90 provides an improved electrical connection between the lower and upper lead frames 20 and 40 respectively.
The solder dipping process is performed after the package assembly process and includes steps such as fluxing, soldering, and cleaning, which can lead to an increase in processing time and a decrease in productivity. Further, the solder dipping process causes a change in the dimensions of the outer lead 47. Such a change may necessitate a modification of the contact pin design of a test socket and a modification in the land pattern design of a module substrate. That is, the outer lead with the solder coating layer cannot use the conventional test socket and module substrate adapted for the outer lead 47.
Further, as seen in FIG. 1, the solder coating layer 90 is deposited more at the curved corners of the outer lead 47 by the solder dipping process. Such portions of the solder coating layer 90 may contaminate the contact pin of the test socket when the outer lead 47 is mechanically contacted with the contact pin. In addition, when the dual-die package 100 is mounted on the module, substrate by soldering, the solder coating layers 90 of the adjacent outer leads 47 may form a solder bridge and cause electrical short-circuiting of the dual die package 100.